Personally I don’t assume we will see the road between memory and storage be all that muddled sooner or later. Yes, 3D XPoint is a lot more responsive than Flash. However Flash isn’t all that spectacular as is. The everyday laborious drive has entry latencies around 4ms on common. Flash can attain nicely bellow µs latency, however for very small arrays. This is costly and principally seen in Microcontrollers that execute immediately from their Flash. "Enterprise grade" flash that optimizes at cost/GB can have far higher latency, in the few to tens of µs region. 3D Xpoint is a bit of a wash. I have seen quoted figures of sub 350ns write latency, but that is likely for a single cell, not an array. Optane modules from Intel alternatively have typical latencies around 5-15µs, but that is from a "system" perspective, ie, protocol and controller overhead comes into play, in addition to one’s software program setting.
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DRAM alternatively has entry latencies around 2-15ns at current. The problem with latency is that it leads to our processor stalling attributable to not getting the information in time. One can prefetch, but branches makes prefetching harder, since what facet must you fetch? Department prediction partly solves this difficulty. But from a performance standpoint, we should always fetch both sides. But when we have extra latency, we have to prefetch even earlier, risking extra branches. In other words, peak bandwidth required by our processor Memory Wave will increase at an exponential rate in comparison with latency. A price that is utility dependent as properly. Caching might seem just like the trivial solution to the problem, however the effectivity of cache is proportional to the latency. To a level, cache is a magic bullet that just makes memory latency disappear. However every time an application requires something that isn’t in cache, then the application stalls, Memory Wave App as long as there's threads to take its place that also have knowledge to work on, you then won’t have a performance deficit apart from thread switching penelties, however in case you don’t have such threads, then the CPU stalls.
One can ensure that more threads have their information by simply making the cache larger, however cache is rather a lot dearer than DRAM. Ultimately, all of it leads to the truth that increasing latency will require an arbitrary quantity more cache for the same system efficiency. Going from the few ns latency of DRAM to the couple of µs latency of current persistent memory will not be real looking as an precise replacement for DRAM, even if it reduces its latency to a a centesimal it remains to be not impressive as far as memory goes. Although, the usage of persistent DIMMs for storage caching or as a "RAM drive" of types nonetheless has main advantages, however for program execution it is laughable. And that i don’t suspect this to alter any time quickly. But I can see a future where the primary memory relocates into the CPU. The place the CPU itself has an HBM Memory Wave App chip or four on it supplying relatively low latency and excessive bandwidth memory to the CPU, while the exterior buses are used for IO and storage. But this isn’t all that real looking in more skilled functions, since some workstation purposes truthfully wants 10’s-100’s of GB of precise RAM to get good efficiency.
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